1. Technical Field
The present invention relates to a test apparatus and a test method.
2. Related Art
An interface is known that is referred to as “source-synchronous,” in which a clock signal is output in synchronization with a data signal. Patent Document 1 describes a test apparatus that tests a device under test adopting such an interface. The test apparatus in Patent Document 1 samples the data value of a data signal using a clock signal output from the device under test, and compares the sampled data value to an expected value.    Patent Document 1: U.S. Pat. No. 7,644,324    Patent Document 2: Japanese Patent Application Publication No. 2002-222591    Patent Document 3: U.S. Pat. No. 6,556,492
There are cases in which the clock signal is not output correctly from the device under test. In such a case, the test apparatus must be able to detect such a defect.